cpu: implement SB/SH/SW
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4654a5bc72
commit
2864b16817
31
cpu.go
31
cpu.go
@ -238,7 +238,36 @@ func (c *CPUState) Step() error {
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case 0b0100011:
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case 0b0100011:
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// SB/SH/SW
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// SB/SH/SW
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panic("todo")
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imm := ((opcode >> 7) & 0b11111) | (((opcode >> 25) & 0b1111111) << 5)
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memAddr := c.Registers[opcode_rs1(opcode)] + imm
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// The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register
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// rs2 to memory.
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funct3 := (opcode >> 12) & 0b111
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switch funct3 {
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case 0b000:
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// SB
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err := c.w.WriteByte(memAddr, byte(c.Registers[opcode_rs2(opcode)]))
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if err != nil {
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return err
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}
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case 0b001:
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// SH
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err := c.w.Write16(memAddr, uint16(c.Registers[opcode_rs2(opcode)]))
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if err != nil {
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return err
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}
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case 0b010:
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// SW
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err := c.w.Write32(memAddr, c.Registers[opcode_rs2(opcode)])
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if err != nil {
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return err
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}
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default:
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return ErrInvalidOpcode{}
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}
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case 0b0010011:
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case 0b0010011:
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// ADDI/SLTI/SLTIU/XORI/ORI/ANDI/SLLI/SLRI/SRAI
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// ADDI/SLTI/SLTIU/XORI/ORI/ANDI/SLLI/SLRI/SRAI
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