2022-12-27 23:12:54 +00:00
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# riscvemu
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An interpreter for the RV32I instruction set.
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2022-12-28 03:07:11 +00:00
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Features:
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- Supports RV32I base instructions only (so far)
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- Page-based virtual memory, with custom memory traps and syscalls
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- Install with Go Modules (`go get code.ivysaur.me/riscvemu`)
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2022-12-27 23:32:49 +00:00
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## License
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ISC License
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The source code includes quotations from the RISC-V Instruction Set Manual under
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the [Creative Commons Attribution 4.0 International License](https://github.com/riscv/riscv-isa-manual/blob/riscv-user-2.2/LICENSE).
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2022-12-27 23:12:54 +00:00
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## References
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- RISC-V Instruction Set Manual: https://github.com/riscv/riscv-isa-manual
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