mappu 49a1f26c06 | ||
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cmd/riscvrun | ||
.gitignore | ||
LICENSE | ||
README.md | ||
cpu.go | ||
cpu_test.go | ||
eei.go | ||
go.mod | ||
virtualEei.go | ||
virtualEei_test.go |
README.md
riscvemu
An interpreter for the RV32I instruction set.
Features:
- Supports RV32I base instructions only (so far)
- Page-based virtual memory, with custom memory traps and syscalls
- Install with Go Modules (
go get code.ivysaur.me/riscvemu
)
License
ISC License
The source code includes quotations from the RISC-V Instruction Set Manual under the Creative Commons Attribution 4.0 International License.
References
- RISC-V Instruction Set Manual: https://github.com/riscv/riscv-isa-manual