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An interpreter for the RV32I instruction set
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mappu b5871337ab cpu.test: add test cases for add, ebreak, assembling fragments with llvm
2022-12-28 15:58:24 +13:00
cmd/riscvrun eei/virtualeei: implement io.WriterAt 2022-12-28 14:11:23 +13:00
.gitignore cpu: separate into cpu/cmd/test/world files 2022-12-28 12:05:26 +13:00
cpu_test.go cpu.test: add test cases for add, ebreak, assembling fragments with llvm 2022-12-28 15:58:24 +13:00
cpu.go cpu: implement ECALL/EBREAK 2022-12-28 14:46:41 +13:00
eei.go cpu: implement ECALL/EBREAK 2022-12-28 14:46:41 +13:00
go.mod initial commit 2022-12-28 11:47:14 +13:00
LICENSE doc: add README.md and ISC license 2022-12-28 12:12:54 +13:00
README.md doc/README: add link to CC-license for source code comments 2022-12-28 12:32:49 +13:00
virtualEei_test.go eei: fixes for write-through pages, endianness 2022-12-28 15:57:49 +13:00
virtualEei.go eei: fixes for write-through pages, endianness 2022-12-28 15:57:49 +13:00

README.md

riscvemu

An interpreter for the RV32I instruction set.

License

ISC License

The source code includes quotations from the RISC-V Instruction Set Manual under the Creative Commons Attribution 4.0 International License.

References