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An interpreter for the RV32I instruction set
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mappu 2864b16817 cpu: implement SB/SH/SW 2022-12-28 14:34:34 +13:00
cmd/riscvrun eei/virtualeei: implement io.WriterAt 2022-12-28 14:11:23 +13:00
.gitignore cpu: separate into cpu/cmd/test/world files 2022-12-28 12:05:26 +13:00
LICENSE doc: add README.md and ISC license 2022-12-28 12:12:54 +13:00
README.md doc/README: add link to CC-license for source code comments 2022-12-28 12:32:49 +13:00
cpu.go cpu: implement SB/SH/SW 2022-12-28 14:34:34 +13:00
cpu_test.go eei: implement paging-based eei 2022-12-28 14:11:07 +13:00
eei.go cpu: implement LB/LH/LW/LBU/LHU 2022-12-28 14:27:12 +13:00
go.mod initial commit 2022-12-28 11:47:14 +13:00
virtualEei.go cpu: implement LB/LH/LW/LBU/LHU 2022-12-28 14:27:12 +13:00

README.md

riscvemu

An interpreter for the RV32I instruction set.

License

ISC License

The source code includes quotations from the RISC-V Instruction Set Manual under the Creative Commons Attribution 4.0 International License.

References